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Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B820F2048IL120 /MSC /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADDRFAULTEN)ADDRFAULTEN 0 (CLKDISFAULTEN)CLKDISFAULTEN 0 (PWRUPONDEMAND)PWRUPONDEMAND 0 (IFCREADCLEAR)IFCREADCLEAR 0 (TIMEOUTFAULTEN)TIMEOUTFAULTEN 0 (RAMECCERRFAULTEN)RAMECCERRFAULTEN 0 (EBIFAULTEN)EBIFAULTEN 0 (WAITMODE)WAITMODE

Description

Memory System Control Register

Fields

ADDRFAULTEN

Invalid Address Bus Fault Response Enable
CLKDISFAULTEN

Clock-disabled Bus Fault Response Enable
PWRUPONDEMAND

Power Up on Demand During Wake Up
IFCREADCLEAR

IFC Read Clears IF
TIMEOUTFAULTEN

Timeout Bus Fault Response Enable
RAMECCERRFAULTEN

Two Bit ECC Error Bus Fault Response Enable
EBIFAULTEN

EBI Bus Fault Response Enable
WAITMODE

Peripheral Access Wait Mode

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data